1. Field of the Invention
This invention relates generally to analog to digital conversion systems and more particularly to a system for removing D.C. offset from a system for converting an analog seismic signal to a digital signal.
2. Description of the Prior Art
The use of analog to digital converter systems to produce a binary digital signal representative of the instantaneous value of an input analog voltage has long been known to the art. In systems used to convert an input seismic signal to a corresponding digital signal, the input signal is normally amplified to increase the signal amplitude prior to applying the signal to the analog to digital converter. Because the amplitude of the analog seismic signal can vary over a wide range, an amplifier is normally employed having a gain which is variable in binary increments. In such systems, a certain amount of DC offset can be expected to be present; that is, with a zero level input signal to the amplifier, the output signal from the digital to analog converter will be offset somewhat from zero. Even if compensation means are included in the system to adjust for offset at any given time, offset will reappear due to temperature changes, component drift and aging. Normally, such systems include elements to continually adjust for offset changes.
Such methods have included chopper stabilized amplifiers, such as disclosed in U.S. Pat. No. 3,988,689, issued Oct. 26, 1976 to Ochi et al. In these types of offset correction systems, the system offset is sampled and stored on a capacitor, and this stored voltage is then applied to subtract the offset from the succeeding amplified signal.
Other methods have included DC feedback around the amplifier, such as disclosed in U.S. Pat. No. 3,636,463 issued Jan. 18, 1972 to Ongkiehong. In such systems, a signal is taken from the output and fed back to the input to reduce offset. The feedback is passed back through a low pass filter to remove the AC component from the feedback.
Other systems employing DC feedback include U.S. Pat. No. 4,308,504, issued Dec. 29, 1981 to Ida and U.S. Pat. No. 4,301,421 issued Nov. 17, 1981 to Yokoyama. These systems use a signal derived from the DC offset voltage appearing at the output terminal to reduce the DC offset voltage. In the first instance, the collector-to-emitter voltages of two bipolar transistors are controlled. These bipolar transistors are connected in series with a differential pair of field effect transistors which comprise the input stage differential amplifier. Controlling the collector to emitter voltages of the bipolar transistors reduces the DC offset voltage. The second system is similar, except that the feedback varies the junction temperature or, alternatively, the voltage across the junctions, of transistors in the differential amplifier in accordance with the magnitude and polarity of an output offset voltage.
U.S. Pat. No. 4,395,681 issued July 26, 1983 to Hornung et al discloses a system in which the amplifier output is compared to a reference voltage in a comparator circuit. The output of the comparator controls an up/down counter, whose output controls a digital to analog converter. The digital to analog converter controls two current sources which vary the input level to the differential input to the amplifier to correct for offset.
U.S. Pat. No. 4,356,450 issued Oct. 26, 1982 to Masuda shows a system in which an offset correcting signal is generated while the circuit input is grounded. The output level is sampled and the count in an up/down counter is varied, depending on the polarity of the output signal. The digital output signal from the up/down counter is converted to a corresponding analog signal by a digital to analog converter and the output from the converter is applied to an input to the amplifier to correct for offset.
Also relevant is U.S. Pat. No. 3,516,085 issued June 2, 1970 to P. K. Dano. This patent discloses a system for shifting the amplitude of the signal which is applied to an analog to digital converter to enable an analog to digital converter having a given input range to encode a signal having variations which exceed that range. The output of the amplifier is continuously sampled by a threshold detector. When the input to the threshold detector exceeds a selected level in either a negative or positive direction, a counter control circuit causes a binary counter to count either up or down and the counter output controls an offset voltage control circuit which, in turn, controls a circuit which applies an offset voltage to the summing junction at the amplifier input to shift the signal amplitude so that it stays within the range of the analog to digital converter.
A primary disadvantage of the chopper stabilized systems is that they depend on a voltage level stored on a capacitor to effect the compensation, and the leakage which will occur from the capacitor will diminish the effectiveness and reliability of the feedback.
A primary disadvantage of the analog DC feedback systems is that the low pass filter will inherently delay the response time.
The systems employing feedback to vary junction temperature or collector-to-emitter voltage have inherent accuracy limitations.
The Hornung et al and Masuda systems utilize the stability of digital feedback, but these systems, like the other prior art systems, compensate for offset in the amplifier only.
The Dano system, while it uses circuitry similar to applicant's invention, is directed toward accomplishing a different objective.
Although systems for correcting for feedback in a binary gain amplifier are known, the prior art does not disclose a system for correcting for offset in the entire analog to digital conversion system; from input amplifier, through the sample and hold circuit and the analog to digital converter. Further, the prior art does not disclose a two step correction system in which a feedback signal is updated periodically to reduce steady state, or slowly varying, offset; and in which short term offset variations are compensated for by grounding the input following each data conversion cycle and generating a digital output signal representing any remaining offset not corrected for by the steady state feedback, and subtracting this offset digital signal from the previously generated digital output signal.